The present invention relates to a fabrication technology of a semiconductor device, more specifically to a semiconductor device having a DRAM-type memory device and a method for fabricating the same.
A DRAM is a semiconductor memory device which can be formed by one transistor and one capacitor. Various structures for DRAMs of higher density and higher integration, and methods for fabricating DRAMs of such structures have been conventionally studied.
Recently in the field of the fabrication of the DRAM-type semiconductor device the competition among makers has become severe, and it is an important subject how to fabricate DRAM-type semiconductor devices of higher integration and higher achievement at low costs.
To this end, the capacitor requires a simpler structure. Structures which are simple and can secure sufficient capacities are studied. One of such structures of the capacitor uses a pillar-shaped conductor as the storage electrode.
A semiconductor device using the pillar-shaped conductor as the storage electrode will be explained with reference to FIG. 52.
On a semiconductor substrate 10 there are formed source/drain diffused layers independent of each other. A gate electrode 18 is formed on the semiconductor substrate 10 between the source/drain diffused layers 20, 22 through a gate oxide film. Thus a memory cell transistor comprising a gate electrode 18, the source/drain diffused layers 20, 22 is formed.
An inter-layer insulation film 24 with a through-hole formed in above the source/drain diffused layer 20 is formed on the semiconductor substrate 10 with the memory cell transistor formed on.
In the through-hole a storage electrode 46 is formed with the bottom connected to the source/drain diffused layer 20 and protruded onto the inter-layer insulation film 24. An opposed electrode 56 is formed on the upper surface and the sidewalls of the storage electrode 46 through a dielectric film 52, and the storage electrode 46, the dielectric film 52 and the opposed electrode 56 constitute a capacitor.
On the semiconductor substrate 10 with the memory cell transistor and the capacitor interconnections 60, 62 are formed trough an inter-layer insulation film 68. The interconnection 60 is connected to the opposed electrode 56, and the interconnection 62 is connected to the semiconductor substrate 10 in a peripheral circuit region.
Thus a DRAM comprising one transistor and 1 capacitor is formed.
As described above, the conventional semiconductor device shown in FIG. 52 has the storage electrode 46 constituting the capacitor in the simple pillar-shaped structure, which can be easily formed by one film forming step and one patterning step. Thus the capacitor forming step can be drastically simplified, and the forming costs can be accordingly lower.
However, in the conventional semiconductor device using the pillar-shaped storage electrode 46 the memory cell region is higher than the peripheral circuit region by a height of the storage electrode 46, which makes it difficult to open a contact hole for connecting the interconnection 62 to a peripheral circuit.
That is, usually a contact hole for connecting the interconnection to the peripheral circuit is formed through the inter-layer insulation film 48 formed on the storage electrode 46 (FIG. 52). However because of a large height difference of the inter-layer insulation film 68 between the memory cell region and the peripheral region, in simultaneously forming the contact hole to be opened on the opposed electrode 56 and the contact hole to be opened in the peripheral region, a sufficient depth of focus cannot be obtained in the contact hole opening step and the metallization step, which required micronized processing precision. Neither of the two contact holes cannot be correctly formed.
To ensure a sufficient depth of focus, the inter-layer insulation film 68 is planarized by, e.g., CMP (chemical mechanical polishing) method. However, the contact hole in the peripheral circuit region has a very high aspect ration, which makes it difficult to open the contact hole. It also makes it difficult to bury the interconnection in the contact-hole (FIG. 53).
To the semiconductor device fabrication process it is important for lower fabrication costs how to decrease lithography steps, and semiconductor structures and methods for fabricating the same which can decrease lithography steps are needed.
Each lithography step needs a pattern layout which considers a alignment allowance. For micronization of the devices, new means which enables the pattern layout to be conducted without considering the alignment allowance is needed.